1. Technical Field
The embodiments described herein relate to a semiconductor memory apparatus, and more particularly to a data strobe clock buffer of a semiconductor memory apparatus, and a method of controlling the same.
2. Related Art
Generally, a semiconductor memory apparatus includes a plurality of data input buffers and a plurality of data strobe clock buffers, which receive data signals and data strobe clock signals, to perform a data input operation. The data strobe clock signals are input in the form of a clock signal pair, and a data strobe clock buffer in the semiconductor memory apparatus buffers the external data strobe clock signals to generate internal data input strobe clock signals. The semiconductor memory apparatus, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), uses the internal data input strobe clock signals generated from the data strobe clock buffer to perform an operation of generating a rising data input strobe clock signal and a falling data input strobe clock signal, thereby strobing data to a rising edge and a falling edge of the external clock.
The data strobe clock buffers operate in response to buffer enable signals. For example, the data strobe clock buffer performs the aforementioned buffering operation during time intervals where the buffer enable signals are enabled and stops the buffering operating if the buffer enable signals are disabled. The buffer enable signals are signals generated using the clock signals in the semiconductor memory apparatus. Accordingly, the semiconductor memory apparatus uses the internal clock signals to generate the buffer enable signals and defines the operation intervals of the data strobe clock buffers using the generated buffer enable signals.
However, as the operational speed of the semiconductor memory apparatus increases, sensitive reaction by the semiconductor memory apparatus to small jitter components of the external data strobe clock signals and the external clocks signals increases. For example, when toggle timings of the external data strobe clock signals are fast or toggle timings of the external clock signals are slow, the ending time of the enable interval of the buffer enable signal is delayed, and the data strobe clock buffer malfunctions by providing output of unwanted data. Such a malfunction causes a circuit region to receive subsequent data that incorrectly recognizes non-data as real data while degrading the stability in the data input operation.
The malfunction is caused by the generation of buffer enable signals without considering that the external data strobe clock signals and the external clock signals have different clock domains. For example, the operations that define the enable time intervals and buffer the external data strobe clock signal are performed using the clock signals having different clock domains. However, the buffer enable signals do not have accurate enable time intervals due to adverse influences, such as the environment and noise. Accordingly, the semiconductor memory apparatus does not stably generate the rising data input strobe clock signals and the falling data input strobe clock signals and are, therefore, vulnerable to data input errors.